Сибирский федеральный университет

Тип публикации: доклад, тезисы доклада, статья из сборника материалов конференций

Конференция: International Conference on Information Technologies in Business and Industry; Tomsk Polytechn Univ, Tomsk, RUSSIA; Tomsk Polytechn Univ, Tomsk, RUSSIA

Год издания: 2018

Идентификатор DOI: 10.1088/1742-6596/1015/2/022019

Аннотация: The article deals with the choice of the architecture of digital signal processing units for implementing the PSK signal detection scheme. As an assessment of the effectiveness of architectures, the required number of shift registers and computational processes are used when implementing the »system on a chip» on the chip. A statistical estimation of the normalized code sequence offset in the signal synchronization scheme for various hardware block architectures is used. © Published under licence by IOP Publishing Ltd.

Журнал: Journal of Physics: Conference Series

Выпуск журнала: Vol. 1015, Is. 2

Номера страниц: 22019

ISSN журнала: 17426588

Издатель: Institute of Physics Publishing

• Sokolovskiy A.V. (Siberian Fed Univ, 79 Svobodny Ave, Krasnoyarsk 660041, Russia)
• Dmitriev D.D. (Siberian Fed Univ, 79 Svobodny Ave, Krasnoyarsk 660041, Russia)
• Veisov E.A. (Siberian Fed Univ, 79 Svobodny Ave, Krasnoyarsk 660041, Russia)
• Gladyshev A.B. (Siberian Fed Univ, 79 Svobodny Ave, Krasnoyarsk 660041, Russia)

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• Web of Science Core Collection
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