Сибирский федеральный университет

Тип публикации: статья из журнала

Год издания: 2016

Ключевые слова: parallel computing, functional programming, high-level synthesis, formal verification

Аннотация: We develop methods and algorithms for a high-level synthesis and a formal verification of the architecture for very-large-scale integration (VLSI). The proposed approach is based on the functional-flow paradigm of parallel computing and enables one to perform architecture-independent VLSI synthesis by the construction of a computing model in the form of intermediate structures of control and data graphs. This approach also provides an opportunity to verify a design at the formal description stage before the synthesis of the register-gate representation. Algorithms and methods are developed for the construction and optimization of an intermediate representation of a computing model, the verification, and going to the register-gate description of VLSI. The stages of the high-level VLSI synthesis are formed in the context of the proposed technique. An example of the synthesis of a typical module is considered for a digital signal processing. Results of the practical modeling are presented for an example.

Журнал: WSEAS Transactions on Computers

Выпуск журнала: Т. 15

Номера страниц: 239-247

ISSN журнала: 11092750

Издатель: WSEAS Press

• Nepomnyashchiy O. (Siberian Federal University)
• Legalov A. (Siberian Federal University)
• Typkin V. (Siberian Federal University)
• Ryzhenko I. (Siberian Federal University)
• Shaydurov V. (Siberian Federal University)

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