Структурный метод уменьшения случайной составляющей погрешности компонентов АЦП : научное издание | Научно-инновационный портал СФУ

Структурный метод уменьшения случайной составляющей погрешности компонентов АЦП : научное издание

Перевод названия: Structural method for reducing random component of ADC components error

Тип публикации: статья из журнала

Год издания: 2019

Идентификатор DOI: 10.18127/j20700784-201901-06

Ключевые слова: аналого-цифровой преобразователь, погрешность, помеха, симметричный тракт, интегральная схема, analog-digital converter, error, interference, symmetrical path, integrated circuit

Аннотация: Предложен метод подавления помех аналогового тракта, основанный на использовании второго измерительного канала, который позволяет осуществить полное симметрирование с помощью второго ЦАП, согласованного по характеристикам с первым, опорным. Исследована модель АЦП с симметричными согласованными трактами. Доказана эффективность предложенного метода. Показано, что предложенный подход позволяет значительно уменьшить интегральную нестабильность результирующей характеристики квантования АЦП. The article considers the reduction of the random component of the instrumental error of analog-to-digital converters (ADCs) by completely balancing the analog-digital path based on the double integral components. The authors propose a method for suppressing the interference of an analogue path using a second measuring channel. Full symmetrization between the channels is provided by the second DAC, which is matched on characteristics to the first, reference DAC. The article describes a developed ADC model with matched symmetric paths. The effectiveness of the proposed method is proved. The proposed approach provides a significant reducing in the integral instability of the resulting ADC quantization characteristic. Modern achievements of microelectronics allow integrating both analog and digital components on a single chip: complex combinational logic, processor, operational amplifiers (OS), comparative devices (SS), key elements, DACs, etc. [1,2,6,7]. This creates the prerequisite for creating single-chip ADC structures that have a complete symmetry of the analog-to-digital conversion path of the relative common wire. At present, measuring transducers with differential inputs are used as symmetrical circuits. Also, dual elements made on a single chip are widely used in circuitry to build operational amplifiers, where due to the high degree of identity and consistent functioning of paired structures, a significant reduction in the influence of interference and drift is achieved [1]. However, the load of such converters is not symmetrical with respect to the common wire and the full compensation effect is not achieved. A solution can be found by using a second measurement path. The complete structural symmetry of the analog-to-digital conversion path is provided by the introduction of the second path, which is performed on the same crystal as the first one. Since the crystal has small dimensions, the main external disturbances, including temperature and time drifts, are applied in-phase to the inputs of the threshold elements. If one path is used as the main one, that is, to apply an input voltage to it, and the second one as a reference one (for example, to apply a reference zero potential to it), then the effect of the integrated interference can be compensated. To do this, you need to subtract the reference code from the reference code of the main path. The control unit (CU) performs the functions of controlling the analog-to-digital conversion process, where Ni is one path count. This method involves the introduction of hardware redundancy in the architecture of promising ADCs, which differs from known architectures with an input differential amplifier. However, this allows full symmetrization of the entire analog-to-digital conversion path by introducing a second DAC identical in characteristics with the first one. Thus, in the analog-to-digital conversion path, compensation is made for the random components of the ADC error caused by the broadband additive interference that occurs at the DAC, SS nodes, and input circuits of the converter. The proposed approach allows to significantly reduce the integral instability of the resulting ADC quantization characteristic due to the high identity of the ADC components performed on a single chip. In the technological process of ADC production, the total costs for additional nodes within the integrated circuit increase insignificantly, since the dual components are realized in a similar way to the single ones. In addition, as part of a complex-functional «system on a chip», the area of the dual ADC occupied by additional modules will amount to one percent [8,9]. The proposed model of ADC with matched paths can serve as the basis for developing the structure of an ADC oriented to execution in the form of a hybrid or programmable analog-digital integrated circuit. This will allow to abandon a number of basic technological methods when developing elements and assemblies for analog-to-digital conversion systems: additional screening, ensuring the quality of supply voltage, and so on.

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Издание

Журнал: Успехи современной радиоэлектроники

Выпуск журнала: 1

Номера страниц: 56-62

ISSN журнала: 20700784

Место издания: Москва

Издатель: Закрытое акционерное общество Издательство Радиотехника

Авторы

  • Гончаров С.В. (ОАО «НПП «Радиосвязь»)
  • Непомнящий О.В. (Институт космических и информационных технологий ФГАОУ ВПО «Сибирский федеральный университет»)
  • Середкин В.Г. (Институт космических и информационных технологий ФГАОУ ВПО «Сибирский федеральный университет»)
  • Постников А.И. (Институт космических и информационных технологий ФГАОУ ВПО «Сибирский федеральный университет»)
  • Хантимиров А.Г. (Институт космических и информационных технологий ФГАОУ ВПО «Сибирский федеральный университет»)

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